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EDA and IP

Codasip platform accelerates CHERI adoption

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Codasip has launched a complete exploration platform to accelerate CHERI adoption. Codasip Prime comprises pre-silicon hardware and software development kits to realise state-of-the-art memory-safe compute. The  platform is based on the Codasip X730 application core, which integrates CHERI (Capability Hardware Enhanced RISC Instructions). Based on commercially available IP, Codasip Prime enables advanced development of memory-safe and secure software. The platform ...

Hardware Pioneers Video: Siemens and Crypto Quantique, discuss secure DFT Architecture

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At Hardware Pioneers Max 2025 we caught up with Lee Harrison, Director of Product Marketing at Siemens, and Dr. Shahram Mossayebi, Founder and CEO of Crypto Quantique, as part of our promotional coverage for the event. They discuss how design for test is a critical part of any semiconductor, but with DFT requirements around the collection of in-life silicon health ...

Crypto Quantique launches lightweight RoT IP block

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Crypto Quantique, a provider of quantum-driven silicon IP and an end-to-end security platform for embedded devices, has announced a new lightweight root-of-trust (RoT) IP block to enable security feature implementation in resource-constrained MCUs and IoT devices. Called QRoot Lite, the implementation complies to the Measurement & Attestation RootS of Trust (MARS) specification developed by the Trusted Computing Group (TCG) as ...

Qualcomm files countersuit against Arm

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Qualcomm has filed a countersuit against Arm for hearing in Q1 2026. Qualcomm claims that Arm has been in breach of contract by misrepresenting the relationship between the two companies to Qualcomm’s customers, non-delivery of IP  and misrepresenting its intentions as a design firm when it was preparing to sell proprietary ICs. Qualcomm also claims that Arm interfered with its ...

US to tackle patent abuse

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Yesterday, the U.S. Patent and Trademark Office (USPTO) announced it is setting up the Patent Fraud Detection and Mitigation Working Group to mitigate threats and protect the integrity of the U.S. patent system. The group will act to limit improper activity in patent applications and reexamination proceedings at the USPTO and reduce patent application pendency. As patent threats continue to ...

IAR adopts subscription model for cloud-embedded tools

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“IAR is transitioning from selling individual products with perpetual ownership to offering our entire toolbox in a platform, as a customer-friendly subscription service,” announced CEO, Cecilia Wachtmeister (pictured). The scalable software design tools include the company’s Embedded Workbench, with C/C++ compiler and the company’s Build tools. IAR C-STAT (for static code analysis) and IAR Embedded Trust (for end-to-end security) and ...

DVCon Europe confirms research papers deadlines

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the organisers of this year’s Design and Verification Conference & Exhibition Europe (DVCon Europe) have announced the deadline for abstracts for engineering papers and tutorials for this year’s event. Abstracts need to be submitted by 22 April, with full engineering and research papers required by 30 June. DVCon Europe will be hosted by Accellera Systems Initiative, and will take place ...

Webinar: Introducing the next-gen FlexIC design platform

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Pragmatic Semiconductor and Electronics Weekly are hosting a webinar: Introducing the next-gen FlexIC design platform: a new era of innovation in flexible electronics. The date and time is: 2nd April 2025 – 15:00 BST | 16:00 CEST | 10:00 EDT Sign up for the FlexIC design platform webinar » It is aimed at IC Designers, ASIC Engineers, and those working ...

Welsh semiconductor design centre

Compound Semiconductor Applications Catapult

A new UK semiconductor design centre is expected to spring from a joint venture between the Welsh Government, the Compound Semiconductor Applications (CSA) Catapult and Cadence Design Systems. “The design centre, which has received £2.5m in Welsh Government investment, funding from Cadence, and support from CSA Catapult, will create over 100 jobs for graduate students in the next five years,” according ...

PAVE360 SDV tech available on AMD CPUs and GPUs on Azure

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Siemens Digital Industries Software announced has expanded the cloud platforms of choice available for systems-of-systems development with its PAVE360 technology for Software Defined Vehicle (SDV) development which is now available on AMD Radeon PRO V710 GPUs and AMD EPYC CPUs running on Azure. Siemens’ PAVE360 development requires graphics acceleration for accurate simulation of scenario realisation, as well as accelerated execution of ...