Ed To Boost UK Semis

The over-build of mature node capacity and consequent foundry utilisation rates of 70-75% present an opportunity to secure future fab capacity at advantageous rates, Ed confides to his diary, and I have set u a fund to do it.

My strategy is to get every UK semiconductor company, design house, university, R&D institute, startup, individual designer or student to come up with either designs or ideas for designs which can use this capacity. HMG can provide access to the latest AI-enabled EDA tools if required.

Key to my plan is to get as many UK designers as possible familiarised with AI-assisted design which can significantly accelerate time-to-market and optimise layout, power, performance, leakage, simulation, verification and efficiency. AI is said to reduce chip design time by 30-50% and accelerate place-and-route by 40-60%.


The combination of a transformative advance in IC design with low fab costs could be a shot in the arm for UK chip entrepreneurs if they can be enabled to take advantage of it. This enablement will now be made available thanks to Yours Truly.


I have set  up a committee to decide which designs and design ideas we will support under the scheme. I shall be the chairman and the other members, who I will appoint, will be my stooges –  so I will be running the show.

 As word gets around that I am gate-keeper to this opportunity, I have no doubt that applications to take advantage of it will be accompanied by some agreeable sweeteners.

David Manners

David Manners

David Manners has more than forty-years experience writing about the electronics industry, its major trends and leading players. As well as writing business, components and research news, he is the author of the site's most popular blog, Mannerisms. This features series of posts such as Fables, Markets, Shenanigans, and Memory Lanes, across a wide range of topics.

Leave a Reply

Your email address will not be published. Required fields are marked *

*