Electronics Weekly
In some cases compile time can be cut by up to 70% through algorithm optimisation and increased parallelisation, said Altera.
The software also includes the Rapid Recompile feature which allows for small source code changes on Altera Stratix V FPGA designs resing previous compilation results to preserve performance, without the need for up-front design partitioning.
“With new capabilities and enhancements to the latest version of the Quartus II software, we are delivering a 2X compile time advantage and a 20 percent performance advantage over the competition with our high-end FPGAs,” said said Alex Grbic, director, software and IP product marketing.
Quartus II software version 13.1 also includes enhancements to the Qsys system integration tool, DSP Builder model based design environment and the Altera SDK for OpenCL.
“Using Qsys, designers can seamlessly integrate a mix of industry-standard interfaces, including Avalon, ARM AMBA AXI, APB and AHB interfaces, for faster system development,” said Altera.
Now there is enhanced system visualization, allowing multiple simultaneous views of the Qsys system.
Altera SDK for OpenCL is now in full production having passed conformance testing by adhering to the OpenCL specification defined by the Khronos Group.
Altera DSP Builder Advanced Blockset systems can now be integrated within MathWorks HDL Coder. Improvements in fast Fourier transform (FFT) processing include variable-sizing of FFTs at run-time and super-sampling FFTs for data rates of 10GHz.
