Tests find one-in-five SRAM upsets may give errors

An investigation into the frequency with which single-event upsets (SEU) caused by high energy neutrons from cosmic events occur in FPGAs has found that SRAM-based devices are affected to a greater extent than either flash or antifuse parts.

The tests also found that between one in five and one in ten configuration upsets in SRAM devices leads to a logic error.

The tests, in which flash, antifuse, and SRAM parts were exposed to a neutron flux equivalent to 7,600 years at sea level, found that the failure-in-time (FIT) rates for SRAM FPGAs were between 300 and 1,100. Commercial integrated circuits typically show FIT rates of under 100, with the target for high reliability applications closer to 20. A FIT is defined as the number of failures in 10⁹ hours.

The likelihood of a neutron disrupting the charge in an SRAM cell is thought to increase as the charge in the cell decreases, for instance as the process geometry shrinks. However, last year leading FPGA supplier Xilinx said it saw a reduced susceptibility to SEUs on moving from 0.13µm to 90nm.

For flash devices, in which the charge is held by a floating gate, the test results showed lower susceptibility to neutron-induced errors.

Barry Marsh, v-p product marketing at anti-fuse and flash-based FPGA firm Actel, said the growing prevalence of FPGAs in production designs meant that designers would increasingly have to bear in mind the potential for neutron induced errors when choosing a part.

“We’re seeing more and more FPGAs being used in production systems, and this is just something else a designer has to think about when he specifies a 0.13µm or 90nm device, he said. For many cases these errors don’t matter, for others, it may be a critical selection priority.”

The investigations, which followed a JEDEC-defined neutron test spec, were made by chip test firm iRoC Technologies at the Los Alamos Neutron Center.