Electronics Weekly
The intention is to target microprocessors and DSPs with deficient or even non-existent JTAG (IEEE Std. 1149.1) boundary-scan test registers.
The debug routines dubbed JTAGLive CoreCommander can be used to activate the on-chip debug (OCD) modes of a range of popular cores to affect ‘kernel-centric’ testing.
The routines can be used for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair, since no on-board code is required to set memory reads and writes.
Boundary-scan deficient parts can also be better utilised during production test, as CoreCommander-driven functions increase fault coverage.
“Since CoreCommander is Python-based it complements perfectly the JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronised testing to full boundary-scan devices,” said the company.
Interactive mode allows the user to select a supported device within a design and ‘manually’ select register access commands or full memory reads and memory writes from the interactive window and via a supported controller to the target design. Sequences of commands can be exported from the interactive window and replayed as part of a Python script.
Python-embedded mode uses a similar structure to that featured in the JTAGLive Script product, allowing CoreCommander functions to be embedded into Python code to create re-usable test modules for specific tests.
