Cadence Design Systems provides industry-leading EDA tools and IP solutions that empower electronics engineers to design advanced semiconductors and systems. Their software supports digital, analog, and mixed-signal design, verification, and packaging. Cadence’s innovations enable AI chip design, RISC-V adoption, and system-level integration. Electronics Weekly highlights Cadence’s new tools, collaborations, and industry impact on accelerating electronics product development.
Madhuparna Datta, of Cadence Design Systems, has joined the UK Electronics Skill Foundation’s (UKESF) board as a Trustee. Currently the Application Engineer Director of Cadence, she has worked in the semiconductor industry for more then 25 years. “We’re thrilled to welcome a new Trustee to the UKESF board,” said Neil Dickins, UKESF Chair of Trustees. “Madhuparna brings vast expertise to ...
DAC 2024: The EDA industry is reaping the rewards of an evolution in the semiconductor and software industries, said Jay Vleeschhouwer, software research analyst at Griffin Securities (pictured). The essential nature of EDA has become more apparent, he said, as semiconductor companies are becoming increasingly like systems companies and systems companies are becoming increasingly like semiconductor companies, he said. Software ...
Cadence has added three apps to its Palladium Z2 emulation hardware for SoCs. “These domain-specific apps allow customers to manage increasing system design complexity, improving system-level accuracy and accelerating low-power verification for applications such as artificial intelligence, machine learning, hyperscale and mobile,” according to the company. They are: Four-state emulation for simulations requiring X-propagation, such as for low-power verification of ...
A PDK for the SkyWater open-source 130 nm process will be available in the Cadence VLSI (very large-scale integration) Fundamentals Education Kit. The kit teaches students how theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor. SkyWater collaborated with Cadence to create an open-source chip manufacturing program ...
A binaural hearing aid system-on-chip prototype has been created by a consortium that including GlobalFoundries, Cadence, Leibniz University Hannover and Hoerzentrum Oldenburg. SmartHeAP, the smart hearing aid processor, is based on Cadence’ Tensilica G6 DSP and LX7 processor intellectual property, designed on Cadence’ flow and made on GloFo’s 22FDX FD-SoI platform – 22FDX has adaptive body bias to save power, ...
Rebecca Dobson is corporate vice-president, EMEA, Cadence Design Systems, following a career in sales with two UK semiconductor companies. She tells Caroline Hayes about her route into electronics and how she led staff through the pandemic. Rebecca Dobson studied for a BsC in business information technology. “I was good at chemistry, so I chose something that gave me options,” she ...
Cadence Design Systems has announced LPDDR5X memory interface intellectual property designed to operate at 8,533Mbit/s, claiming it to be the first. Based on its LPDDR5 and GDDR6 products, the IP has a PHY and a controller, designed to follow the JEDEC JESD209-5B standard. The controller-PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses ...
Cadence has announced a design tool for IC design sign-off. Called Certus closure solution, the “environment automates and accelerates the complete design closure cycle, from sign-off optimisation through routing, static timing analysis and extraction”, said Cadence. “The solution supports the largest chip design projects with unlimited capacity.” It lists these attributes: Distributed hierarchical optimisation and sign-off architecture for cloud and ...
Cadence has announced artificial intelligence driven verification applications that use ‘big data’ to “optimise verification workloads, boost coverage and accelerate root cause analysis of bugs”, according to the company. Together called the Verisium platfom, the suits are is built on another of the company’s platforms: JedAI (joint enterprise data and AI). “The release of Verisium represents a generational shift from ...
Cadence has unveiled intellectual property for two DSP, aimed at asics for radar, lidar and communications processing. Called ConnX 110 and ConnX 120, the blocks share the instruction set of the existing ConnX B10 and B20 DSPs. The 110 version offers 128bit SIMD for math operations based on 8, 16 and 32bit fixed-point and half-, standard- and double-precision floating-point. The ...
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