Support for multi-threading acceleration for CPUs with multiple physical cores is provided by the CacheQ Compiler which takes a single-threaded C code and generates executable that can run on CPUs, accelerating executing by 486% on x86 processors with 12 cores, reports CacheQ Systems (based on benchmarks from the Black Scholes financial algorithm). There is no need for manual code rewriting, threading ...
Bus-based scan data distribution architecture enables true bottom-up DFT flows, writes Geir Eide of Siemens Digital Industries Software. The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs ...
Cadence is claiming up to 3x transient simulation performance for its latest transistor-level circuit simulator, compared with its previous offering. Called Spectre FX Simulator, it is the next generation of the company’s ‘FastSpice’ branded products, aimed at pre and post-layout verification of large DRAM, flash, SRAM and transistor-level SoC designs. “Design teams can verify functionality and timing for sign-off in a productive manner,” according to ...
Infineon has announced machine learning extensions to its ModusToolbox for deep learning workloads on its PSoC microcontrollers. “Enabled by TinyML, ‘artificial intelligence of things’ is a natural evolution, where acting on data locally helps manage data privacy, latency and overall system reliability,” said Infineon v-p IoT Steve Tateosian. “ModusToolbox bridges a gap between machine learning and embedded systems design by ...
Agile Analog of Cambridge has closed a $19m funding round led by Canadian pension company Omers Ventures, and backed by existing investors Delin Ventures, firstminute capital and MMC Ventures. “What excites us about Agile Analog is the potential for scale,” said Omers partner Henry Gladwyn. “Every other analogue IP supplier is restricted to selling a limited range of standard IP ...
RS Components introduced version 10.0 of its two PCB design packages: DesignSpark PCB and DesignSpark PCB Pro. Changes to free-of-charge DesignSpark PCB include: disconnect from signal nets option component-to-component SMT check output drill data to Gerber library item time stamps improvements to the new component wizard Pay-for DesignSpark PCB Pro gets those changes, and also: intelligent backups new design rule checks ...
Crypto Quantique is a London company created to licence technology that provides end-to-end encrypted security for embedded systems. Its products include a hardware root-of-trust, which has already been licenced to a “a big semiconductor company for a high-end MCU”, according to company co-founder and CEO Shahram Mossayebi (pictured). Mossayebi should know about security: he has an MSc in information security and ...
Alphawave, the Canadian wired connectivity IP specialist, is to IPO seeking to raise $500 million cash at a valuation of $4.5 billion. BlackRock and Janus Henderson have committed to take $510 million worth of shares at an equity valuation of up to $4.5 billion. Alphawave plans to sell at least a quarter of its shares at the IPO. CEO and ...
Cadence is aiming at high-end and always-on applications with DSP intellectual property for embedded vision and AI. There are two cores: Vision Q8 for multi-camera automotive and mobile markets 1,024bit SIMD and 3.8Top/s 2x performance and memory bandwidth compared with the Vision Q7 Vision P1 for always-on and smart sensor consumer applications, as well as AR and VR glasses. 128bit ...
The organisers of DAC have opened nominations for the 2021 Marie R. Pistilli Women in Electronic Design award. This award recognises people who have advanced women in electronic design and is named after the DAC organiser. Last year’s recipient, Cadence’s engineering group director, automotive, Alessandra Nardi, was profiled in the 12 August issue of Electronics Weekly. Nominations can be submitted ...
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