A new take on the concept of digital twins was announced by Nvidia at its developer conference in San Jose this week, as founder and CEO, Jensen Huang announced that the company’s Omniverse Cloud will be available as APIs (application programming interfaces). Customers will be able to use these APIs to design, simulate, test and build physically based digital twins ...
Arteris is supporting Armv9 automotive cores and ASIL D functional safety with release 3.6 of its Ncore cache coherent network-on-chip. “In 2020, Arteris announced a partnership with Arm and the alignment of our roadmaps to support CHI-E and ASIL B and ASIL D safety,” Arteris told Electronics Weekly. “We confirm the expansion of that partnership with a pre-validation of our ...
Siemens EDA has announced three products, for emulation, evaluation and software prototyping for data centres and servers. The Veloce CS consists of the Strato CS hardware, for emulation, the Primo CS hardware for enterprise prototyping and proFPGA CS hardware for software prototyping. According to the company, the hardware-assisted verification and validation system can accelerate verification and validation cycles by up ...
Imec has launched an early-access process design kit for the N2 (2nm ICs) node. “The PDK will enable virtual digital designs in imec’s N2 technology, including backside power delivery network,” according to the Belgion semiconductor research lab. “This will give academia and industry the tools to train the semiconductor experts of tomorrow and enable the industry to transition their products ...
Protecting against IP theft, and to prevent contract manufacture hardware counterfeiting, ‘FPGA Lock’ from Nial Stewart Developments is an intellectual property block for FPGAs that communicates with Microchip’s SOT-23 ATSHA204A crypo-authentication IC. The cores uses generic Intel altsyncram and Xilinx 7 series blockram macros and occupies ~720 registers and two ram blocks. Only one pin on the FPGA is needed, ...
Taiwanese SoC design house Faraday Technology is collaborating with Arm and Intel on a 64-core system-on-chip, intended to be made with Arm Neoverse data-centre-grade cores using Intel’s 18A (nominally 1.8nm) foundry process – the latter due to become available at the end of this year. It will use Arm Neoverse Compute Subsystems (CSS, pictured), where “Arm delivers validated, performance-optimised compute ...
SignatureIP is offering a trial of its processor agnostic network-on-chip (NoC) configuration software. Called iNoCulator, the “tool enables users to find the optimal NoC configuration, and the company believes that it is the fastest on the market”, it said. “This try-before-you-buy offer will enable engineers to see for themselves just how easy it is to design a NoC with our tool.” ...
Cadence has added three apps to its Palladium Z2 emulation hardware for SoCs. “These domain-specific apps allow customers to manage increasing system design complexity, improving system-level accuracy and accelerating low-power verification for applications such as artificial intelligence, machine learning, hyperscale and mobile,” according to the company. They are: Four-state emulation for simulations requiring X-propagation, such as for low-power verification of ...
Synopsys is expanding its Synopsys.ai EDA suite to bring GenAI across the full stack to improve engineering productivity for the semiconductor industry. This expands upon Synopsys’ recent announcement to deliver Synopsys.ai Copilot, the first in a series of GenAI capabilities for chip design. Early collaborations with AMD, Intel, and Microsoft have substantiated the power of generative AI for chip design. ...
Amazon may be in a tight spot in its video streaming technology dispute with Nokia, but there are options, writes John-Paul Rooney, a consumer tech specialist at European intellectual property firm Withers & Rogers. News that tech innovator Nokia is suing Amazon in five jurisdictions – the UK, Germany, India, the European Unified Patent Court, and the US – for ...
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