24Gbit/s UCIe chiplet-to-chiplet IP demonstrated at 3nm

Alphawave Semi has unveiled 3nm UCIe (universal chiplet interconnect express) die-to-die communication intellectual property, which has been demonstrated with TSMC’s chip-on-wafer-on-substrate (CoWoS) packaging.

“This complete PHY and controller subsystem, developed with TSMC [using] TSMC’s CoWoS 2.5D silicon-interposer-based packaging, delivers a bandwidth density of 8Tbit/s/mm,” said Alphawave. It supports “PCIe, CXL, AXI-4, AXI-S, CXS, and CHI, features live per-lane health monitoring, and operates at 24Gbit/s”.

The test chip has been validated against UCIe specifications, across typical, slow and fast process conditions, across design voltage and across design temperature, and it meet margins for link, TXIO, and RXIO loopback, according to the company, which added that it complies with UCIe rev 2.0, and includes JTAG, BIST, DFT and KGD (known good die) capabilities.

Applications are foreseen in hyperscale data centres, high-performance computing.

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Steve Bush

Steve Bush is the long-standing technology editor for Electronics Weekly, covering electronics developments for more than 25 years. He has a particular interest in the Power and Embedded areas of the industry. He also writes for the Engineer In Wonderland blog, covering 3D printing, CNC machines and miscellaneous other engineering matters.