Electronics Weekly
“Networking chips are now the biggest chips out there – they can be bigger than 20x20mm and have more than 400 million gates,” says Brunet. “Simulation is insufficient because of the limit to cycles per second. Emulation accelerates the verification process by one million times over simulation.”
“The current approach is not scalable, ” adds Brunet, “we need a scalable solution to one billion gates – there’s a need for lab virtualisation.”
Which is why Mentor has launched the Veloce VirtuaLab Ethernet environment, with support for 25G, 50G and 100G Ethernet. This support enables efficient, emulation-based verification for the massive Ethernet-based designs being created today.
The huge surge in demand for connectivity has had a profound effect on the size of switch and router designs, making them among the largest IC designs developed today.
The sheer size of the designs, the pressure for early release, and the need to verify all paths are creating a methodology shift that moves verification from simulation- to emulation-based flows, according to Mentor. 
VirtuaLab Ethernet replaces the physical devices used in In-circuit Emulation (ICE) with virtual devices, so moving emulation from the engineering lab to the computing datacenter for maximum emulation resource utilisation.
VirtuaLab components provide a software-driven Ethernet stack that runs at up to 15,000 times the speed of traditional simulation, the company says.
The accelerated deployment of VirtuaLab solutions in the networking market is the result of improvements in throughput. Whereas in simulation it’s not uncommon to run 1,000 packets of data per day, in emulation “customers report they are running 11,000,000 packets of data per day”, says Mentor.
The Veloce emulation platform is a technology in the Mentor Enterprise Verification Platform (EVP).
