Circuit design

Harvard University PhD student Wonyoung Kim is looking for venture capital to help fund a semiconductor intellectual property (IP) startup with the aim of putting greater control over power on SoCs, according to Dan Nenni writing at Semiwiki. The technology behind the startup made its public debut at the International Solid State Circuits Conference (ISSCC) this year: it was a ...

One of the more counter-intuitive aspects of low-power design is temperature dependence. Traditionally, things have always got worse as they heat up. Leakage power goes up; delays increase. But when you deal with low-power, high threshold-voltage (Vt) cells, the effects can go in reverse, as Abhishek Mahajan and Sorabh Sachdeva of Freescale Semiconductor point out in a piece they’ve written ...

Near-threshold logic offers a lot of promise for low-power design as it can switch with very little energy, just as long as you can afford the drawback of it being very sloooowwww. It’s not helped by the fact that it’s often hard to tell how slow without actually building test circuits. In a presentation at the recent International Symposium on ...

Mainstream CMOS process development is a little like Highlander: there can be only one. It matters which choices other chipmakers make because they will control how quickly the industry as a whole can get down the yield learning curve – and how much the end product costs. It is possible to use more exotic processes but these really only succeed ...

As part of a session on security at the Design Automation Conference (DAC) in San Diego last week, Intel engineer Ram Krishnamurthy talked about designing cryptographic circuits using near-threshold voltage transistors – that quadratic relationship between supply voltage and energy still counts for a lot. However, it’s easy to see why this type of circuit design remains a specialty. Near-threshold ...

For the past ten years, clock gating has been one of the main weapons in the low-power designer’s armoury. Power gating operates conceptually in the same area: disable logic paths when there no activity. But both techniques tend to concentrate on the control sections of logic blocks. To get power down further, we now have the prospect of the low-power ...

System-on-chip (SoC) devices now have a lot of memory on them – often more than 50 per cent of the die area is now given over to embedded memories according to members of Samsung India’s ASIC design group, based in Bangalore. Writing at Design & Reuse, Akilesh Mahaja, Naveen Tiwari and Raghuram P reckon that the memories can also account ...

The Design Automation Conference, which returns to San Diego this year, is now less than a month away and has put together a programme that includes coverage of low-power design issues. Tuesday 7 June has a panel that attempts to work out who in the design chain can make the biggest savings, from device physicists to systems and software engineers. ...

In days of yore, one process used to fit them all. Then CMOS processes split into high-power (HP) and low-power (LP) process options. As 3D transistors such as the finFETs that Intel will deploy at 22nm become more common, we can expect even more options to appear.

One of the curious features of low-power circuits in advanced processes is that the lower-voltage option does not always lead to the best overall design. Very often the hare strategy, in which you run circuits as fast as possible and then shut them down, works out better than the slow, steady and somewhat leaky tortoise strategy of running much more ...