MSP430 clones explore limits of MCU power

In 2008, a team from the Massachusetts Institute of Technology (MIT) demonstrated a design based on a version of the MSP430 architecture. In separate work, TI and MIT worked together to develop a 0.6V near-threshold DSP that also got its first showing at ISSCC last year. Led by veteran TI engineer Dennis Buss, the company has run its own research project on sub-threshold circuitry – he talked about a 0.3V version of the MSP430 at the International Electron Device Meeting (IEDM) last December. At this year’s ISSCC, however, it was the Catholic University of Leuven that made its own addition to the list of sub- or near-threshold versions of the MSP430, but with a twist. Only the microprocessor core itself runs at very low Vt, and that’s because it’s switched off most of the time. The trouble with near-threshold devices is that leakage dominates the power consumption. That problem is not helped by the fact that sub- or near-threshold transistors are far from fast, so they tend to have to remain switched on for longer than their higher voltage brethren. However, the active power is so low that, if you can tolerate the cycle times, the trade off is worth it. And, applications that use devices such as the MSP430 tend to have very low duty cycles – so they have plenty of time to get things done and still spend 99 per cent of their time asleep. Memories and always-on logic such as real-time clocks are more problematic as they can consume a lot of power in subthreshold form and, in the case of memories, not work that well. However, their activity factor is low, so the amount of power they consume when switching is less noticeable even if they use relatively high suppy voltages. So the Leuven group used a tweaked 65nm process – one that made it possible to use the gate oxides from both low-power and general-purpose versions of the process – to implement memories, clocks and other constantly ready – if not entirely active – circuits. This cut overall leakage compared with a pure near-threshold implementation without increasing active power too much. They also worked on reducing another major source of active power draw – accesses to instruction memory – by adding a small instruction cache. It has just 32 entries but as a lot of code runs in tight loops, this is enough to cut a lot of the capacitive load usually incurred by fetching instructions from main memory. Because the arrays are quite large, this power can be significant even when dealing with on-chip capacitances. The 32-entry cache imposes its own power overhead because it needs to run without imposing a cycle time penalty on a cache miss. It turned out that this was the optimum size from a power trade-off point of view as it slashed memory accesses by 80 per cent or so. Doubling its size would not have increased this ratio significantly but would have almost doubled the power draw of the cache itself as the memory array capacitance increased. According to David Bol and colleagues from Leuven, the combination of techniques used on the MSP430 clone allowed operation at clock frequencies similar to those of commercial versions but with an energy efficiency three-times higher than the 65nm MIT design from four years ago.