Electronics Weekly
In February this year, Silexica and Xilinx co-presented at the International Symposium on FPGA, elaborating on the new SLX plug-ins which is designed to extend the capabilities of Xilinx’s Vitis HLS. The HLS compiler add-on provides a Loop Interchange pragma to improve Vitis HLS latency. The event saw the two companies demonstrate how the SLX plug-in and XLX FPGA worked together with the Vitis platform to adopt an HLS methodology. The SLX FPGA tool suite tackles non-synthesisable C/C++ code, non-hardware-aware C/C++ code, the detection of application parallelism and pragma insertion location to optimise C/C++ application code and determine optimal software and hardware partitioning.
Salil Raje, executive vice president and general manager, Data Center Group, Xilinx, commented on the synergy between the two companies: “Silexica’s technology complements our existing Vitis solution and roadmap and will accelerate our ability to attract a wider range of developers seeking to leverage our heterogeneous computing architectures.”
Maximilian Odendahl, former CEO of Silexica, and now senior director of Adaptive Computing at Xilinx, said: “The integration of our technology with the Xilinx Vitis portfolio fully aligns with our goal of making adaptive computing accessible to software developers. We are excited to continue the journey as part of the Xilinx Vitis team.”
Financial details and the terms of the transaction are not being disclosed.
