Lending a hand to Armv9

Earlier this year, Arm released its first new architecture in 10 years. Caroline Hayes looks at what Armv9 brings and what design support is available.

The Armv9 architecture targets secure operation, with Confidential Compute Architecture and performance for AI, machine learning (ML), digital signal processing (DSP) and capabilities with an evolution of Scalable Vector Extension (SVE) technology, created with Fujitsu for the Fugaku supercomputer.

Businessman hand using mobile phone with digital layer effect as business strategy concept

SVE2 is claimed to enhance the processing abilities of 5G systems, virtual reality (VR) and augmented reality (AR) and ML workloads running locally on central processing units (CPUs), and has announced that Armv9 will see CPU performance increases above 30% over the next two generations of mobile and infrastructure CPUs.


The architecture applies across all of Arm’s IP portfolio (automotive, client, infrastructure and IoT) and the company says it is already developing technologies to increase frequency, bandwidth, and cache size, and reduce memory latency for Armv9-based CPUs.


EDA partnerships

Early adopters were able to implement Armv9 in SoCs using Cadence’s digital and verification flows. Customers have taped out SoCs for mobile applications using Cadence tools with Arm Cortex-X2, Cortex-A710 and Cortex-A510 CPUs, Mali-G710 GPUs and the DynamIQ Shared Unit-110. In collaboration with Arm, Cadence has “fine-tuned” its digital and verification full flows on 5nm and 7nm process technologies for the Armv9 architecture. It has also delivered 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to enable customers to achieve optimal power, performance and area and accelerate time to tapeout.

Integrated RTL-to-GDS RAKs include the Cadence Modus DFT software, Genus synthesis, Innovus implementation system, Quantus extraction, Tempus timing signoff and ECO option, Voltus IC power integrity, conformal equivalence checking and conformal low power.

Cadence has also optimised its System-Level Verification IP (System VIP) and verification full flow to support the latest Arm advanced microcontroller bus architecture protocols for rapid adoption of Armv9 IP while accelerating integration and functional signoff of Arm mobile SoCs. Cadence System VIP extensions for Armv9 include new checkers, verification plans and traffic generators to efficiently verify Arm mobile SoC coherency, performance and Arm SystemReady compliance.

The verification full flow for the Armv9 IP includes the Xcelium logic simulation platform, Palladium Z1 and Z2 enterprise emulation platforms, Protium X1 and X2 enterprise prototyping platforms, JasperGold formal verification, manager planning and metrics and Perspec system verifier and virtual system platform.

“Over the years, we’ve closely collaborated with Arm across verification, implementation and system design to enable our mutual customers to realise their SoC designs… across markets such as AI, mobile, and high-performance computing,” said Anirudh Devgan, president of Cadence. “Our optimised digital flows have demonstrated early successes, showcasing the power and performance benefits of the Armv9 architecture.”

First-pass silicon

Another partner, Synopsys, has also announced first-pass silicon, SoC tapeouts for Arm Cortex-X2, Cortex-A710 and Cortex-A510 CPUs based on Armv9 as well as Mali-G710 GPUs and DynamIQ Shared Unit-110.

The two companies have collaborated for 30 years. “Access to the Armv9 architecture and [Synopsys’] . . . Fusion design and verification continuum platforms, enables our mutual customers best power, performance and area, quality-of-results, and time-to-results,” asserted Sanjay Bali, vice-president of product marketing at Synopsys.

“We look forward to continuing our collaboration on the next generation of challenges including 3D IC design, machine learning and smart process, voltage and temperature monitoring,” he added.

According to Synopsys, the early SoC tapeouts capitalise on Arm’s architectural innovations and jointly developed flows and methodologies targeting the latest 5-nm, 4-nm and 3-nm process technologies. It says that the fusion verification continuum and DesignWare Interface IP provide a software-to-silicon solution to maximise performance per Watt across various use cases, including specialised AI, DSP, VR and AR.

Early adopters are using Synopsys’ verification continuum platform solutions optimised for Arm, including Virtualizer development kit with Arm Fast Models for Cortex-X2, Cortex-A710, Cortex-A510 CPUs and Mali-G710 GPUs, VCS simulation, Verdi for hardware and software debug, Verification IP for the latest Arm AMBA interconnect, ZeBu server and HAPS hardware to accelerate hardware-software bring up and power and performance validation, Synopsys reported.

QuickStart implementation kits include implementation scripts and reference guides that enable early adopters to accelerate time to market and achieve performance per Watt targets.

Electronics Weekly asked Siemens Digital Industries Software about Armv9 tools and Kathleen Tufto, senior product manager, embedded platform solutions, said: “Our embedded operating systems and associated software tools will support Armv9, just as we currently support Armv8, and have supported previous versions in the past.”

EW Staff

Leave a Reply

Your email address will not be published. Required fields are marked *

*