Electronics Weekly
Rupert Baines
“Our IP is JTAG on steroids,” Baines told Electronics Weekly, “the IP goes onto the die at the design stage in the form of blocks implemented in the SoC. The blocks help you debug, they get the hardware working and they get the software working with the hardware.”
“Our IP is much more sophisticated and richer than JTAG, ” added Baines, “it’s universal, it works with all flavours – and whereas JTAG comes out of a serial port and can take ages, ours can mux through USB so it’s very much faster and doesn’t need dedicated pins.”
UltraSOC’s IP comes as either a hard or a soft macro and can be parameterised. It has macros to support all standard processors and can analyse all standard logic.
A customer has done 3 ICs using UltraSOC’s IP and is currently ramping into volume.
‘It can get a chip done faster and makes the chip work better in the world,” said Baines, “UltraSoC has a great team and game-changing technology. We’re not only empowering designers to create better products ‘first-up’, more quickly and easily – we’re also giving them the opportunity to use connectedness and analytics to refine the performance and features of those products when they’re actually in use. This really has never been possible before.”
UltraSoC’s core offering embeds debug and analysis capabilities into the silicon chips that are used in today’s electronic products. This allows chip designers to design and debug their devices more quickly, and to offer their customers innovative features such as in-service power consumption optimisation, self-testing and failure detection.
Although a Cambridge-based start-up, UltraSOC’s technology originated from Essex University.
UltraSOC is backed by Octopus – the VC company which backed Zoopla and Secret Escapes
