Electronics Weekly
“Everyone is talking up their angle,” Rowen told EW, “the Asic guys are saying if you try and do your own designs you won’t get first time right silicon; the EDA people are trying to get you to believe it is worth spending tens of millions of dollars to verify a chip; the mask people are happy to let you believe it costs millions of dollars for a mask set.”
For instance IBM has said the first-time-right rate on 0.13µm for the semiconductor industry generally is 50 to 60 per cent, but the foundry industry is only getting a five to ten per cent first-time-right rate. While Fujitsu has said the fabless/foundry model starts failing at 0.13µm and below because of the difficulty of matching design to manufacturing capability.
“I would say Broadcom. Xilinx, Altera and Qualcomm have actually done OK,” responded Rowen, “good fabless companies create good design
The $2m projected mask cost of a 90nm SoC has frightened many people. “Mask cost has been everyone’s favourite example,” said Rowen, “mask yield is always very low in the early stages of a new technology – it can drop by a factor of four during the lifetime of a node. When 90nm starts selling widely – two years from now – masks won’t cost $2m. There’s a huge economic incentive in the system to drive mask cost down.”
Asked how many 90nm designs he expected to see manufactured this year, Rowen replied: “My guess is that something like a hundred 90nm designs will be prototyped this year.” He added: “It’s possibly premature to say 0.13µm is mature. I’d say probably 0.18 or 0.25[µm] is mature.”
