Electronics Weekly
Chips take too long to make to keep up with fast-moving algorithm development is Van den hove’s central thesis.
“There is a huge inherent risk of stranded assets because by the time the AI hardware is finally ready, the fast-moving AI software community may have taken a different turn,” Van den hove will say, reports Reuters, which has seen a copy of his speech.
Van den hove sees chip design becoming based on multi-functional supercells containing all necessary capabilities for AI processing. “A network-on-chip will steer and reconfigure these supercells so they can be quickly adapted to the latest algorithm requirements,” Van den hove is expected to say.
The chips will be made using 3-D stacking with multiple layers of memory and logic. Hybrid electronics-photonics integration, phase-change alloys, novel transistor architectures and sub-2nm processes may also be needed.
Sticking to the current approach to AI chip development will mean that companies like the hyperscalers, which develop their own custom chips tailored to their own workloads, could find the usefulness of their hardware developments outdated by fleet-footed software developers.
See also: Imec and ASML sign five year R&D agreement
